1. Field of the Invention
The present invention relates to semiconductor processing technology and, in particular, concerns an electronic module comprised of multiple chip stacks assembled into a single electronic package having improved heat dissipation.
2. Description of the Related Art
Semiconductor manufacturers continually strive to increase the packaging density of integrated circuit chips, which has led to the development of high-density electronic packaging modules such as three-dimensional multi-chip structures. Multi-chip structures typically comprise a plurality of integrated circuit chips that are adhered together in a stack so as to reduce the amount of space that the chips occupy inside a system. Typically, each chip in the stack has a plurality of conductive input/output contacts that are exposed on at least one lateral surface of the chip. The exposed contacts provide conductive interconnection between the chips in the stack and external circuitry.
As a result of the increased device density of VLSI (Very-Large-Scale Integration) and ULSI (Ultra-Large-Scale Integration) integrated circuitry, wiring interconnective metallurgy between input/output terminals of stacked integrated circuit chips has become increasingly more complex. A higher packaging density likely requires an increase in the number of conductors, which likely reduces the space between adjacent conductors. Unfortunately, such dimensional reductions tend to increase the capacitance between adjacent conductors, thereby possibly increasing signal propagation delays and signal cross-talk. The limitations brought about by capacitive coupling between adjacent conductors has become a significant impediment to achieving higher wiring density.
The capacitive coupling effect is particularly apparent in high-density electronic packaging modules, such as three-dimensional multi-chip structures. In some multichip structures, the conductive leads on the integrated circuit chips are closely spaced, and adjacent leads may sometimes be separated by less than 1 micron. Consequently, reducing the distance between adjacent leads may adversely impact the functionality of the multi-chip structure due to an increase in the capacitive load between adjacent conductors. In addition, stacking the chips in close proximity to one another as required in multi-chip structures may also increase the capacitive coupling effect between conductors of adjacent chips.
Many integrated circuit chip designers have tried to address the problem of increased capacitive coupling between adjacent conductors by utilizing insulative materials that have lower dielectric constants than conventional dielectrics such as silicon-dioxide (SiO2). which has a dielectric constant of about 4.5. In some cases, polymers, such as polyimides, which have a dielectric constant of about 2.8-3.5, have been used in place of SiO2. However, the polyimides provide limited improvement for the capacitive coupling problem and, therefore, do not provide a significant advantage in use.
Alternatively, interconnects incorporating an air bridge structure have also been developed and are described in prior art references such as U.S. Pat. No. 5,891,797 to Farrar. Air bridge structures generally comprise suspended conductors that are surrounded by an air gap instead of the more conventional insulators. For example, U.S. Pat. No. 5,324,683 to Fitch et al. describes the formation of an air bridge structure in an integrated circuit by removing all or a portion of the dielectric layer between conductors so that the conductors are surrounded and insulated by an air gap. Air has a dielectric constant of approximately 1.0, which is substantially less than the dielectric constants of conventionally used insulators such as SiO2 or various polymides. As such, the air-gap insulator provides some improvement for the capacitive coupling effect associated with the increased wiring density of integrated circuit chips.
Although air bridge structures permit an increase in the integrated circuit wiring density, the use of air bridges introduces some new problems such as the effective removal of heat from the air bridge structures. Generally, increasing the integrated circuit wiring density leads to a decrease in the cross-sectional area of the conductors. As the cross-sectional area of an air bridge conductor decreases, the electrical resistance of the conductor increases, which results in an increase of the operating temperature of the conductors.
Excessive heat generation is particularly apparent in high-density multi-chip electronic packages, such as multi-chip modules or three-dimensional multi-chip structures. As the number of components in a multi-chip electronic package increases and the packaging density becomes more compact, the ability of heat to dissipate efficiently diminishes, which increases the risk of self-overheating and may reduce the reliable life of the semiconductor device. Moreover, integrated circuit and device functional characteristics may also depend on ambient temperature within the multi-chip electronic package. Therefore, as the ambient temperature of the package increases due to excessive heat generated by the conductors, hot spots within the multi-chip electronic package may form and adversely affect the performance of the integrated circuit.
Hence, from the foregoing, it will be appreciated that there is a need for an electronic module having higher wiring density combined with an efficient cooling system that effectively removes heat from the module. What is proposed herein is a densely packed electronic module having improved heat dissipation efficiency and a process of manufacturing the same.